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2007

www.leti.fr

FIB/SEM Dual beam :FEI Expida 1285300 mm FOUP & 200 mm Open CassetteSEM column : Sirion (3 nm resolution)FIB column : Sidewinder (low kV thinning)Beam Chemistries:

Tungsten deposition SiO2 deposition Insulator enhanced etch

Nanolift option (TEM sample preparation & transfer): ChunkWizard - Omniprobe - TSU

X-Ray Analysis (Oxford)

TEM :FEI Tecnai G² F20 STWIN TMPVoltage : 200 kVElectron Source : FEG

TEM point resolution : 0.24 nm TEM line resolution : 0.14 nm STEM resolution : 0.20 nm

2kx2k GATAN CCDX-Ray Analysis (EDAX)

9 - First TEM Observation00:30; 20%

1 - Wafer loading (inclunding : area of Interest

localization and electron assisted W deposition

protective layer)

00:15; 10%

2 - Sample milling(5x5 µm)

00:15; 10%

3 - Lift out(sample extraction)

00:15; 10%

4 - Capsule Loading 00:05; 3%

5 - Sample transfer to TEM grid00:10; 7%

6 - Thinning00:40; 27%

7 - Capsule Unloading00:05; 3%

8 -Transfer to TEM 00:15; 10%

In-line transmission electron microscopy for micro and nanotechnologies R&D

V. Delaye, F. Andrieu, F. Aussenac, O. Faynot, R. Truche, C. Carabasse, A. L. Foucher, A. DanelCEA-LETI, MINATEC, 17 rue des Martyrs, 38054 Grenoble Cedex 9 France

Phone: +33 (0)4 38 78 40 08 e-mail: vincent.delaye@cea.fr

IntroductionAdvanced microelectronics, micro and nanotechnologies characterizations needs :

Reduced cycle time (cost) High resolution imaging and analysis of materials and structures with

nanometers dimensionsAn adapted tool is Transmission electron microscope (TEM), but :

Dedicated for off-line laboratories Destructive Delicate and time consuming sample preparation

To meet the needs of such R&D facility, as much in term of cycle time as resolution :

Full 200 and 300 mm wafer FIB-SEM dual beam system for sample preparation (100 nm thick lamella)

200 kV TEM installed close to dual beam and inside cleanroom.

2h30 to 6h00 hours/sample

200 & 300 mm wafers

TEM samples

In-line TEM resolutionThe microscope supplier (FEI) specifications are all achieved in dedicated area except for 50Hz (60dB instead of less than 54 dB) acoustic level. However : Resolution tests in TEM and STEM modes have been successfully conduced with the FEI Tecnai S-Twin 200 kV microscope installed.

Preparation to observation flowStarting from wafer loading in the dual beam to TEM picture delivery : A cycle time between 2h30 and 6h00 hours has been obtained depending on the sample size and the lamella thickness required.

This flow includes : Electron beam assisted tungsten protective layer deposition to reduce

surface damage to 1 nm instead of 30 nm with ion beam Low-kV (5kV) ion beam final thinning for less than 100 nm lamellas

(nanometer gate oxide measurement for example)

Wafer return for front-end levelsAn other major concern in R&D and manufacturing semiconductor industry is to reduce wafer costs due to destructive characterization. It has been already shown that sample preparation impact on wafer is limited to 1 mm around the FIB crater; such impact allows the industry (1) to re-introduce wafers after TEM sample extraction at back-end levels.

Dedicated TEM area inside the cleanroom : Anti-vibration TMC table Acoustical walls Adapted lighting conditions Adapted air conditioning flows Magnetic field canceling system

Time management for

a 5x5x0.1µm lamella

NMOSL1B

PTGL250

To go further, we made 2 samples extractions (common gate pattern NMOSL1B L=70nm and isolated transistor PTGL25 W=50nm) at 3 front-end process levels on two FDSOI (Fully Depleted SOI) wafers to study the impact on electrical performances.

The device extraction does not affect the electrical performance of all the devices further than 500 µm (from another pattern in the same die). On NMOSL1B common gate pattern, devices of the whole pattern are completely scrapped. On PTGL250 isolated transistors other devices, from 180 to 400 µm, on the same pattern work (even if, with degraded performance) except for Step 2.

This new result confirms the localized impact of a FIB extraction around the crater for advanced front-end levels.

Wafer mapping

(11 e-beam dies)

Die description with

the 2 localized patterns

SEM image from isolated PTGL250

transistors pattern with FIB crater zoomElectrical tests results

-0,54

-0,52

-0,5

-0,48

-0,46

-0,44

-0,42

-0,4

-0,38

-0,36

-0,34

VT

(V

)

Max

Min

VT

D01

D03

D04

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

Gm

(µ

S/µ

m)

Max

Min

gm

D01

D03

D04

0.14 nm line resolution

HR-TEM Si 110 HR-STEM Si 110

Chunk milling Probe welding Chunk lift-out FIB crater

Transfer to grid Chunk approach

Sample preparation to observation flow example

Chunk view Thinned chunk

FIB sample preparation

Sample

transfer

TEM analysis

Inline TEM Dedicated Cleanroom Area

200 & 300 mm

Lots wafers

TEM sample preparation

using FIB/SEM

DualBeam

TEM/STEM sample imaging and EDX(1(1stst analysis) analysis)

D01

D02 D03

D04D05

D06

D07

D08

D09

D10

D11

D01

D02 D03

D04D05

D06

D07

D08

D09

D10

D11

W=0.07µm300 µm from W=0.04µm

W=0.10µm405 µm from W=0.04µm

W=0.15µm360 µm from W=0.04µm

W=0.25µm405 µm from W=0.04µm

W=0.03µm180 µm from W=0.04µm

W=0.04µmSite location

W=0.05µm180 µm from W=0.05µm

W=0.07µm300 µm from W=0.04µm

W=0.10µm405 µm from W=0.04µm

W=0.15µm360 µm from W=0.04µm

W=0.25µm405 µm from W=0.04µm

W=0.03µm180 µm from W=0.04µm

W=0.04µmSite location

W=0.05µm180 µm from W=0.05µm

PTGL250 transistors : Voltage threshold

PTGL250 transistors : Transconductance

FDSOI Transistor

FIB/SEM TEM

Metal gate

Ste

p #

Lev

el

Des

cri

pti

on

Nu

mb

er o

f L

ift-

ou

t

Waf

er

(slo

t )

Fro

m a

12

waf

ers

lot

Die

(s)

Tra

ns

isto

r

Ele

ctri

cal

test

(o

ther

dev

ice

s ar

ea a

nd

die

s)

Ele

ctri

cal

test

(s

ame

dev

ices

ar

ea)

PTGL250 Vt Step 1

After active area patterning

2 11 01 & 03 NMOSL1B

PTGL250 Step 2

During gate stack formation

2 12 01 NMOSL1B

PTGL250 Vt Step 3

Before extension formation

2 12 04 NMOSL1B

> 5

00µ

m

< 5

00µ

m

Conclusion : No measured impact die to die Reduced impact within a pattern, but depending on following process step

200 and 300 mm wafers can be re-introduced within the process flow

Applications : step by step analysis, process monitoring, defectivity.

ACKNOWLEDGMENTS :

The authors would like to thank FEI Company for assistance and support. This work has been carried out, in the frame of CEA-LETI / ALLIANCE collaboration and STMicroelectronics.

REFERENCE :

(1) : BICAIS-LEPINAY N. and al., Proceedings of SPIE vol. 6152, 2006.