MATERIALS SCIENCE &

ENGINEERING g

E L S E V I E R Materials Science and Engineering B29 (1995) 21-23

Analysis of SIMOX metal-oxide-semiconductor transistors operated in the high temperature range

T. Ouisse a, G. Reichert a, S. Cristoloveanu a, O. Faynot b, B. G i f f a r d b

"Laboratoire de Physique des Composants gl Semiconducteurs (URA-CNRS 840), ENSERG, BP257, 38016, Grenoble Cedex, France

~'LETI (CEA-Technologies AvancOes), DMEL-CENG 85X, [:38041 Grenoble Cedex, France

Abstract

A systematic investigation of the physical properties and performance of SIMOX silicon-on-insulator (SOl) meta l -oxide- semiconductor field effect transistors, operated from 210 to 625 K is presented. It is shown that SOI devices are attractive candidates for minimizing leakage currents at high temperature. The surface mobility follows conventional behaviour. The sensitivity of the SIMOX buried oxide to hot carrier injection is found to exhibit a maximum at an intermediate temperature, around 400 K.

Keywords: High temperature; Semiconductor devices; Silicon-on-insulator; Hot carrier injection

1. Introduction

In today's microelectronics industry, the need for integrated circuits rated well beyond the classical limit of 125 °C is emerging in areas such as automotive applications, avionics or oil prospection. The tempera- ture range of silicon integrated components may be extended substantially by using silicon-on-insulator (SOI) devices [1]. Indeed, SOI metal-oxide-semicon- ductor field effect transistors (MOSFETs) have three main advantages over their bulk Si counterparts: reduced leakage currents, absence of thermally acti- vated latch-up and smaller variation in the threshold voltage with temperature [1]. Moreover, they also offer the possibility of operation at very low temperature, which is not possible using wide band gap materials. The aim of this paper is to present a comprehensive view of device performance and reliability in the range 200-625 K, for both fully depleted (FD) and partially depleted (PD) SOI MOSFETs. The buried oxide reli- ability is emphasized.

The Si film thicknesses of the FD and PD devices were t~i = 80 and 200 nm respectively. The front gate and buried oxide thicknesses were 17 nm and 380 nm. The channel lengths ranged from 0.4 to 1/am. Further technological details may be found in Refs. [2-4].

0921-5107/95/$9.50 © 1995 - Elsevier Science S.A. All rights reserved SSI)I (1921-5107(94)04042-7

2. Device performance

The leakage currents increase by six orders of mag- nitude in the temperature range 25-345 °C (Fig. 1). For all devices, the leakage current is dominated by a diffusion-related component, with an activation energy roughly equal to the band gap Eg (1.1 eV). With an accumulated back channel ( Vg 2 = - 35 V in Fig. 1) and in the 420-620 K temperature range, the leakage is still reduced, as would be expected, but below 420 K thermal generation seems to prevail, with an activation energy of Eg/2. At high drain voltages, the activation energy of the p-MOSFET lies between Eg and Eft2.

~- 10 -4 ] O - S

10 -6

10 -7

~ 10 8 o 10 -g

10 ,o

10 " 1 0 -12

1 0 -,3

Fig. 1. Leakage

• / PD VD=-5V n PD Vo=SV

n -FD VD=5V

/- - 3 5 V ~ VG2

L = I H,m - ~ "~

1 .5 2 . 0 2 .5 5 . 0 5 .S

I O 0 0 / T (K -~)

current as a function of reciprocal temperature.

22 T Ouisse et al. / Materials Science and Engineering B29 (1995) 21-23

The subthreshold swing increases to about 200 mV per decade at 200 °C and 260 mV per decade at 300°C. The threshold voltage decreases almost linearly with temperature, the slope being approxi- mately - 2 m V K ~and - 1 . 5 m V K ~ for n-channel PD and FD MOSFETs respectively. For FD devices, such a slope should be improved by using a higher doping level [1 ]. At 345 °C, the difference between the threshold voltages of the p- and n-channel devices was still equal to 0.5 V.

The surface mobility/~ was extracted from the plot of Id/gm 1/2 (Fig. 2). In all devices, kt0 follows very closely a T J.5 law, as usually observed in MOS inver- sion layers. However, when the opposite interface is maintained in accumulation (~2 = - 35 V, Fig. 2), a T-1 dependence is observed. This is in accordance with the theoretical derivation of mobility, using a one- subband model and phonon scattering [5]. In our case (~2 = - 3 5 V ) , quantization should effectively be enhanced by a stronger transverse electric field, thus limiting the intersubband scattering which is usually invoked to explain a steeper dependence o f /~ on it:

3. Reliability

It is now well established that SIMOX buried oxides (BOX) contain numerous electron traps, which can be evidenced either by radiation exposure [6,7] or hot- carrier injection [4,8,9]. These trapping centres probably originate from a substoichiometry in oxygen of the buried insulator. Although these electron traps do not play a crucial role in n-channel MOSFETs, they can be a limiting factor in p-channel MOSFETs [4]. Indeed, for p-MOSFETs, electrons generated by impact ioniza- tion near the drain drift towards the back interface. Part of these electrons are injected into the BOX and captured by the electron traps. This electron trapping may in turn induce noticeable variations in the front channel properties, via interface coupling effects [4].

Such a drawback can be minimized by reducing the supply drain voltage [9]. It is thus of interest to assess the BOX sensitivity to hot carrier injection as a func- tion of temperature. In the remainder, p-channel devices were stressed under normal operation condi- tions (i.e. with a front channel activated), and the back threshold voltage Vt2 was extracted with the front channel accumulated, in order to estimate the charge trapped in the BOX.

An empirical law describes the whole injection pro- cess as a function of different biases [4]:

A V~ ~ = U,, exp( - V~J U~ ) ln ( t ) - r,, exp(V,,/U, ) (1)

where U~, U2, U 1 are constants corresponding to a given technology and r, is a characteristic time con- stant, of order 0.5 s. Aging experiments have been con- ducted from - 62 °C to + 350 °C. Fig. 3 shows typical A Vt2 shifts as a function of time. In contrast with con- ventional hot carrier degradation, the impact of the trapped charge on the threshold voltage increases with temperature (roughly speaking, the decrease in electron mean free path with temperature should reduce hot carrier injection). As can be seen from Fig. 4, AVe2 increases with temperature in the range 210-400 K, and decreases above this temperature. This means that the worst case of degradation does not correspond to the lowest temperature, and must be assessed at an intermediate temperature. The decay rate U 0 of the logarithmic curve does not seem to change substantially over the whole temperature range. However, the characteristic time constant decreases regularly with temperature, and then increases. From these experiments, it is inferred that the influence of temperature can be accounted for empirically by expression (1), just by introducing the temperature dependence of r0. In the lower temperature range, r~j was found to be thermally activated, with E~,-~ 173 meV.

1 09 7

E t~

co 0

L~ LP <( LL £~

Lf]

1 0 0 0

5 0 0

100

FD n-channel von

5V

PD / ~ channel

PD p channel

2 0 0 5O0 1 0 0 0 TEMPERATURE T (K)

Fig. 2. Surface mobility/~o vs. temperature.

8 SOl p-MOSFET 1=0.Sum

7 stress conditions: T=458K Vo~=-2V VD=-SV Y

6 VG2-OV . ~ . _ ~ 275K 5

I 218K

2 598K

0 . . . . . . . ~ ' ' ' ~ . . . . . . . . . . . . . . . . . . . . . . . . . .

10 -' 1 10 10 2 10 ~ 10 4 STRESS TIME (s)

Fig. 3. Back threshold voltage shift during front channel operation.

T. Ouisse et al. / Materials Science and Engineering B29 (199.5) 21-23 23

8 SOl p-MOSFET IG=O.Eum 7 o

0 o

~ 5 ~ 4 >

t 5 stress conditions:

> 2 Vc~=-2V Vo=-EV 0 1 VG2=OV 1000s

0 200 500 400 500 600 700

TEMPERATURE T (K)

Fig. 4. Back threshold voltage shift vs. temperature, after hot carrier stressing.

ized near the drain at low T, acts therefore as a channel shortening on the static characteristics, and thus makes Gmax2 increase. For the highest temperature, attenua- tion of the degradation may be explained by two dif- ferent phenomena: (i) a reduction in the fraction of carriers which are effectively injected into the BOX, and (ii) thermal emission from the traps, which may compete with the trapping process. From the point of view of hot carrier reliability, this means that the SIMOX buried oxide should be suitable for the 600 K temperature range.

4. Conclusion

5O 40 ~ o SOl p-MOSFET IG=O,Eum

, ¢ 30 ~ stress conditions:

© "w" X Vcl=-2V VD=--EV 20 ~ VG2=OV lO00s

\ lO (_9

J - l o 200 500 400 500 600 700

TEMPERATURE T (K)

Fig. 5. Back channel transconductance shift vs. temperature, same conditions as in Fig. 4.

The anomalous behaviour of the A 1/,2 shift with T can be related to the evolution of back channel trans- conductance. In contrast with the A Vt2 shift, the lower the temperature, the higher is the increase in transcon- ductance (see Fig. 5). This indicates that at low temper- ature, the trapped charge is probably located closer to the drain end and/or under the spacer area. In this case, the influence of the trapped charge on V~2 would be attenuated, even though the total amount of trapped charge is higher. Furthermore, this charge, more local-

SOI MOSFETs have strongly reduced leakage cur- rents at high temperature, and are suitable for the 600 K temperature range. In the 300-600 K range, the mobility follows a usual T ~.s behaviour. However, when the back channel is accumulated, a T-1 law is observed, resulting probably from a lower inter- subband transition rate. The SIMOX buried oxide is still reliable at 600 K. For p-channel devices, hot carrier degradation of the BOX exhibits a maximum around 400 K.

References

[1] J.P. Colinge, Silicon-On-Insulator Technology: Materials' to VLS1, Kluwer, Boston, MA, 1991.

[2] O. Faynot et al. Microelectron. Eng., 19 (1992) 807. [3] T. Ouisse et al. J. Appl. Phys., 74(1993) 408. [4] T. Ouisse et al. Microelectron. Eng., 19 (1992) 473. [5] T. Ando et al. Rev. Mod. Phys., 54 (1982) 473. [6] J.L. Eeray et al. IEEE Trans. Nucl. Sci., 35(1988) 1355. [7] T. Ouisse et al. Electron Devices Lett., 12 ( 1991 ) 312. [8] T. Ouisse et al. Electron Devices Lett., 12 (1991) 290. [9] E. Guichard et al. Proc. ESSDERC'93, Grenoble, 1993,

p. 825.