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Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit A. Maouad a,b , A. Homann a , A. Khoury b , J.-P. Charles a, * a Centre Lorrain d’Optique et d’Electronique des Solides, Sup elec, 2 rue Edouard Belin, 57070 Metz, France b D epartement de Physique, Universit e Libanaise, Fanar, BP 90 656, Jdeidet, Lebanon Received 1 November 1999 Abstract Insulated Gate Bipolar Transistors are devices integrating a MOSFET and a bipolar transistor in a Darlington configuration. These devices have been studied before and after conduction stress. During high temperature operations (200°C) hot carriers can induce degradation in gate oxide, at silicon–oxide interface and into the base–emitter junction. The used IGBT SPICE sub-circuit can describe electrical aging in dynamic and static operation. The knowledge of which parameters are influenced during specific functional stress permits us to compensate for these changes or improve the implementation of the component in a circuit, as well as its use in field conditions. Ó 2000 Elsevier Science Ltd. All rights reserved. 1. Introduction The insulated gate bipolar transistor (IGBT) was added to the family of power devices to overcome the high loss of power in the conduction state of MOSFETs. The IGBT is a hybrid device that combines the advan- tages of a MOSFET (high switching speed and low power drive requirement) and a bipolar junction tran- sistor (BJT) (low conduction losses) [1]. The IGBTs have switching characteristics that are very close to those of the power MOSFETs, without sacrificing the superior conduction characteristics of IGBTs. They oer advan- tages over MOSFETs in a high voltage, hard-switching applications. These advantages include lower conduc- tion losses and a smaller die area for the same output power. The smaller die area results in a lower input capacitance and a lower cost. In high voltage MOS- FETs, the power dissipation is mostly due to the con- duction losses; the switching losses being negligible up to 50 kHz. Due to the IGBTÕs higher usable current den- sity, the same power dissipation in the IGBT and MOSFET results in higher junction temperature for the IGBT, because of a higher junction to case thermal re- sistance. The total power dissipation is composed of both conduction and switching losses. The degradation of electrical characteristics due to conduction stress re- sulting in a temperature increase are studied here. A simplified SPICE model [2], defined as a sub-circuit based on an IGBT equivalent circuit, is used to simulate this aging, and a good agreement is obtained with the measurements. The aim of this article is to show, how changes due to extreme stress conditions can be modeled with our SPICE sub-circuit. 2. Stress conditions and measurements The purpose of this work is to study the degradation of the electrical characteristics due to the conduction stress. The stress conditions are chosen to simulate functional degradation under industrial operating con- ditions, so as to perform an accelerated aging. Auto- motive, aerospace industry, oil-well business, military, industrial, chemical, and consumer electronics show in- creasing requirements in higher operating temperatures, exceeding even the mil-specified limit of 125°C. High Microelectronics Reliability 40 (2000) 973–979 www.elsevier.com/locate/microrel * Corresponding author. Tel.: +33-467-413975; fax: +33-387- 759601. E-mail address: [email protected] (J.-P. Charles). 0026-2714/00/$ - see front matter Ó 2000 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 0 ) 0 0 0 0 2 - 0

Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

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Page 1: Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

Characterization of high-density current stressed IGBTs andsimulation with an adapted SPICE sub-circuitA. Maouad a,b, A. Ho�mann a, A. Khoury b, J.-P. Charles a,*

a Centre Lorrain d'Optique et d'Electronique des Solides, Sup�elec, 2 rue Edouard Belin, 57070 Metz, Franceb D�epartement de Physique, Universit�e Libanaise, Fanar, BP 90 656, Jdeidet, Lebanon

Received 1 November 1999

Abstract

Insulated Gate Bipolar Transistors are devices integrating a MOSFET and a bipolar transistor in a Darlington

con®guration. These devices have been studied before and after conduction stress. During high temperature operations

(200°C) hot carriers can induce degradation in gate oxide, at silicon±oxide interface and into the base±emitter junction.

The used IGBT SPICE sub-circuit can describe electrical aging in dynamic and static operation. The knowledge of

which parameters are in¯uenced during speci®c functional stress permits us to compensate for these changes or improve

the implementation of the component in a circuit, as well as its use in ®eld conditions. Ó 2000 Elsevier Science Ltd. All

rights reserved.

1. Introduction

The insulated gate bipolar transistor (IGBT) was

added to the family of power devices to overcome the

high loss of power in the conduction state of MOSFETs.

The IGBT is a hybrid device that combines the advan-

tages of a MOSFET (high switching speed and low

power drive requirement) and a bipolar junction tran-

sistor (BJT) (low conduction losses) [1]. The IGBTs have

switching characteristics that are very close to those of

the power MOSFETs, without sacri®cing the superior

conduction characteristics of IGBTs. They o�er advan-

tages over MOSFETs in a high voltage, hard-switching

applications. These advantages include lower conduc-

tion losses and a smaller die area for the same output

power. The smaller die area results in a lower input

capacitance and a lower cost. In high voltage MOS-

FETs, the power dissipation is mostly due to the con-

duction losses; the switching losses being negligible up to

50 kHz. Due to the IGBTÕs higher usable current den-

sity, the same power dissipation in the IGBT and

MOSFET results in higher junction temperature for the

IGBT, because of a higher junction to case thermal re-

sistance. The total power dissipation is composed of

both conduction and switching losses. The degradation

of electrical characteristics due to conduction stress re-

sulting in a temperature increase are studied here.

A simpli®ed SPICE model [2], de®ned as a sub-circuit

based on an IGBT equivalent circuit, is used to simulate

this aging, and a good agreement is obtained with the

measurements.

The aim of this article is to show, how changes due to

extreme stress conditions can be modeled with our

SPICE sub-circuit.

2. Stress conditions and measurements

The purpose of this work is to study the degradation

of the electrical characteristics due to the conduction

stress. The stress conditions are chosen to simulate

functional degradation under industrial operating con-

ditions, so as to perform an accelerated aging. Auto-

motive, aerospace industry, oil-well business, military,

industrial, chemical, and consumer electronics show in-

creasing requirements in higher operating temperatures,

exceeding even the mil-speci®ed limit of 125°C. High

Microelectronics Reliability 40 (2000) 973±979

www.elsevier.com/locate/microrel

* Corresponding author. Tel.: +33-467-413975; fax: +33-387-

759601.

E-mail address: [email protected] (J.-P. Charles).

0026-2714/00/$ - see front matter Ó 2000 Elsevier Science Ltd. All rights reserved.

PII: S 0 0 2 6 - 2 7 1 4 ( 0 0 ) 0 0 0 0 2 - 0

Page 2: Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

temperature operations such as those at 200°C, taking

account of environmental temperatures as well as self-

heating of the electronics, can be reached during a lim-

ited period and with reduced performance, for standard

silicon technology. For discrete silicon devices speci®ed

below 100 W, one expects a temperature limit of about

250°C. The device undergoes a more severe degradation

for such high operating temperatures at a low gate bias

[3]. The performance and lifetime of semiconductor de-

vices are very sensitive to these upper temperature limits

even so, in any applications, the highest temperatures

occur in extreme situations for periods of the order of

100 h in the life cycle [4].

IRGBC20S from International Recti®er, standard

IGBT type 600V-20A, were stressed using the exper-

imental setup shown in Fig. 1 with VCC� 12.0 V,

IAK� 5 A, RC� 0.5 X. The gate voltage was varied from

0 to 7.0 V, allowing case temperature to be increased up

to 155°C. Any higher temperature value leads to com-

ponents destruction. Tested components were main-

tained under these extreme stress conditions for 1 h to

simulate a long period of standard utilization.

Figs. 2±5 show the typically measured current±

voltage characteristics obtained before and after stress.

No such signi®cant changes in the characteristics were

found for any subsequent stress or longer stress duration.

This result shows that we have reached a saturation in

device degradation [5] as the hot-carrier-induced inter-

face traps form a potential barrier that repels subsequent

hot carriers from causing further damage. Associated

changes in series resistance and in carrier mobility in the

channel region will be discussed further.

The variation of IAK versus VGK for VAK� 0.8 V

(Fig. 3) was used to detect any change in the IGBT

operation due to aging. This graph helps also to select

the gate voltage value corresponding to an open channel

operating condition, i.e. VGK P 6:5 V.

The operating condition VGK� 7 V has been selected

to obtain the I±V characteristics of the emitter±base

junction in the pnp bipolar transistor (Fig. 4) corre-

sponding to the substrate/epi junction shown in Fig. 6.

Fig. 1. The experimental setup circuit for stressing the IGBT,

as well as, for taking the measurements needed to obtain all the

graphs (during stress we use RC� 0.5 X, when measuring

characteristics we use RC� 1 X).

Fig. 2. Collector current versus collector voltage for di�erent

®xed values of the gate voltage, measured before and after

stress.

Fig. 3. Collector current versus gate voltage for a 0.8 V ®xed

value of the collector voltage, measured before and after stress.

Fig. 4. Collector current versus collector voltage for a 7.0 V

®xed value of the gate voltage, measured before and after stress.

974 A. Maouad et al. / Microelectronics Reliability 40 (2000) 973±979

Page 3: Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

Fig. 5 is used to determine the threshold voltage, Vth,

4.9 V before stress changing to 5.2 V after stress.

Standard switching characteristics were determined

before and after stress and are presented in Table 1.

These values di�er from the manufacturerÕs speci®ca-

tions due to the di�ering test conditions. In our case, a

low current±voltage operating point is chosen so as to

characterize the stress through the variations of the

physical parameters included in the model elements.

3. IGBT SPICE sub-circuit

The combined top perspective and cross-sectional

views, not to scale, of one from the thousands of cells the

IGBT comprises are shown in Fig. 6. Its structure is

similar to that of a vertical double di�used MOSFET

(VDMOSFET) with the exception that a p-type, heavily

doped substrate, replaces the n-type drain contact of the

conventional VDMOSFET. Analytical models already

exist [6]. Their implementation sets many problems due

to the complexity of the equations used for calculating

the current and charges of the IGBT. Some authors [7]

propose simpli®ed equations, but the simulation results

show inaccurate results near limit or non standard op-

erating conditions. Another solution is to translate the

physical equations into electrical circuits with original

solutions to replace the derivative functions and other

operators [8], but this solution requires a speci®c SPICE

version such as Interactive Graphics SPICE (IG-

SPICE).

The complete sub-circuit of the IGBT [2] is given in

Fig. 7. The core of this sub-circuit is the IGBT equiva-

lent circuit marked with a bold type face, i.e., a pnp

bipolar transistor driven by an n-channel MOSFET in a

pseudo-Darlington con®guration. This core has been

completed with some components to help simulate var-

ious mechanisms, governing the behavior of the IGBT

Table 1

Comparison of the measured values for the internal bipolar

transistor (Q1) gain, switching times, as well as the life duration

of the minority carriers in the nÿ layer, before and after stress

Before

stress

After

stress

Measurement

conditions

b 1.80 1.55

tr (ns) 330 490 IC� 2.5 A

tf (ns) 460 430 VCC � 5 V

tdon (ns) 55 55 VG � 7 V

tdoff (ns) 80 100

s (ns) 178 172

Fig. 7. Complete sub-circuit of IGBT. The IGBT equivalent

circuit, a pnp bipolar transistor driven by a n-channel MOSFET

in a pseudo-Darlington con®guration, is marked with a bold

type face.

Fig. 6. Combined top perspective and cross-sectional views,

not to scale, of one from the thousands of cells the IGBT

comprises.

Fig. 5. Square root of collector current versus gate voltage for a

5.0 V ®xed value of the collector voltage, measured before and

after stress.

A. Maouad et al. / Microelectronics Reliability 40 (2000) 973±979 975

Page 4: Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

under DC and dynamic operations, such as direct and

reverse breakdown, latchup, switching parameters, etc.

3.1. DC model of IGBT

The transfer characteristics of an IGBT and a power

MOSFET are similar apart from a shift due to the built-

in potential of the base±emitter junction of the pnp bi-

polar transistor. Indeed, the IGBT current is equal to

the MOSFET one multiplied by the current gain of the

pnp bipolar transistor. Therefore, several static param-

eters of the IGBT depend on the SPICE parameters of

the MOSFET.

In our study, the SPICE models used for the BJT and

the MOSFET are the Gummel Poon and the Shishman

Hodges models, respectively. The SPICE parameters

which provide the adjustment of saturation current,

conductivity, and static saturation voltage of the IGBT

are Kp (transconductance coe�cient), W and L (channel

width and length, respectively), GAMMA (bulk

threshold parameter), PHI (surface potential), and

LAMBDA (channel-length modulation) for the MOS-

FET element, and, the current gain for the BJT.

3.2. Dynamic model of IGBT

After calibrating the static parameters, one can pro-

ceed to the dynamic model. Typical dynamic parameters

used to characterize the IGBT are the switching char-

acteristics times tr (rise time), tf (fall time), tdon (turn-on

delay time), tdoff (turn-o� delay time), ton (turn-on time),

and toff (turn-o� time), with

ton � tr � tdon; toff � tf � tdoff :

The biggest limitation to the turn-o� speed of an

IGBT is the lifetime of the minority carriers in the nÿ epi

layer, i.e., the base of the pnp bipolar transistor. The

charges stored in the base produce a characteristic ÔtailÕin the current waveform of an IGBT at turn-o�. When

the MOSFETÕs channel turns o�, electron current de-

creases and the IGBT current drops rapidly to the level

of the hole recombination current at the inception of the

tail. As the base current of the pnp bipolar transistor

corresponds to the MOSFET drain current, the current

gain of the pnp transistor is then, given by [1]

b�Q1� � IC=IMOS:

This current gain corresponding to the BF parameter

of the pnp transistor (Q1 in Fig. 7) in SPICE, is therefore

related to the fall time value (tf ) , as well as the TF

parameter.

Two branches, with components names indicated as

GD and DG in the sub-circuit, between the gate and the

drain of the MOSFET, are used to simulate its dynamic

parameters [9]. Because of the particular structure of the

IGBT, where the gate metalization covers a big part of

the MOSFETÕs drain (nÿ layer), the gate-drain capaci-

tance CGD is the main cause of the turn-o� delay time

[10]. In addition, the CGD is the capacitance of a MOS

structure, its value is the function of the gate voltage.

This capacitance is the equivalent capacitance of the

oxide capacitance Cox and of the depletion drain

capacitance CGDd. The equivalent sub-circuit used here is

a ®xed capacitance CGDmax, representing Cox and a diode

DGD used because the diode transit capacitance due to

the space-charge region has the same behavior as the

CGDd. Two MOSFET transistors, MGD and MDG, con-

trolled, respectively, by the gate±drain voltage EGD and

EDG can switch alternatively to CGDmax or CGDd. The

SPICE parameters of MGD and MDG are chosen to be

that of an ideal MOSFET, in order not to disturb the

working sub-circuit. Therefore, the turn-o� delay time,

tdoff , can be adjusted by the value of CGDmax and the

SPICE parameters of the diode DDG. The turn-on delay

time ®tting can be obtained by adjusting the SPICE

parameters of the MOSFET. These parameters are the

capacitors CGBO (gate-bulk overlap capacitance/channel

length) and CGSO (gate±source overlap capacitance/

channel width). The turn-on delay time tdon increases as

these capacitance values increase.

The parameters of the MOSFET (M1 in Fig. 7) in the

sub-circuit allowing to adjust the rise time (tr) are mainly

Kp (transconductance coe�cient) and IS (bulk pn satu-

ration current). As Kp is used to regulate the static

characteristics, we especially use IS to regulate the tr.

3.3. Parameters determination

The SPICE parameters of the sub-circuit for the

IRGBC20S are determined so as to make the calculated

characteristics ®t to the measurements before stress. The

SPICE model parameters that have been changed from

their default values are given in Table 2.

4. Results and discussion

Measurements in Fig. 2 show a drop in the main

current indicating a drop in transconductance. This is

con®rmed by the measurements of b (Table 1). But a

drop of 15% of b is not su�cient to justify a drop in the

current which attains 50%. Necessarily Kp is surely de-

creases by a much greater percentage. This is also con-

®rmed by the increase in the measured rise time (tr) from

330 to 490 ns after stress (Table 1).

Another con®rmation of transconductance decrease

is given in Fig. 5, where we have a graph showing the

square root of the measured anode±cathode current as a

function of gate-cathode potential for VAK >�VAK�saturation. In this graph, the slope in the linear region

976 A. Maouad et al. / Microelectronics Reliability 40 (2000) 973±979

Page 5: Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

is proportional to [11] the product Kp�b� 1�. We notice

that this slope decreases by 50%. Kp depends on the

normalized oxide capacitance and on the mobilities of

carriers in the N-channel MOSFETs. Devices during

stress support fairly the high temperatures (155°C) and

variations of the characteristics are observed. A decrease

of Kp is due to a decrease in the carrier mobility, l, in the

channel as C(V) measurements performed in accumu-

lation show no variation of the oxide capacitance.

We also notice an increase in the threshold voltage

(Vth) from before to after stress (Fig. 5)

�Vth�before � 4:9 V; �Vth�after � 5:2 V:

This increase also explains the drop in the static satu-

ration current observed in Fig. 2, and it is an indication

that the interface oxide-semiconductor charge has a

greater e�ect than that of the oxide, since

DVth � DVNit � DVNot, knowing that DVNot is always

negative [12]. Where DVNit is the voltage variation due to

the interface traps charge, and, DVNot is the voltage

variation due to the oxide charge.

Fig. 4 shows the variations of the current±voltage

measurements for the P�Nÿ substrate±epi junction be-

fore and after aging. The threshold conduction voltage

of this junction is not altered by the stress, but the slope

after conduction decreases. This is related to an increase

of the series resistance of the junction. This change can

be attributed to an increase in the resistance of the

epitaxial layer RNÿ and therefore would indicate the in-

troduction of density defects in the volume [1], or to the

decrease of the mobility in the fully open channel of the

MOSFET, as shown above.

The stress associated to the chosen switching condi-

tions induce a degradation of the IGBT performances.

We can notice that the fall time (tf ) has improved and

that the life duration of the minority carriers in the Nÿ

layer (s) has decreased from 178±172 ns after stress

(Table 1). The degradations are related to a recombi-

nation increase within the bulk and a decrease in the

transconductance due to an enhancement of interface

and oxide trapped charges.

The results obtained by the SPICE simulation are

given by four graphs (Figs. 8±11), which are similar to

the graphs obtained from the measurements (Figs. 2±5).

Table 3 presents the SPICE parameters which have been

adjusted to make the simulated curves ®t the measured

Fig. 8. Collector current versus collector voltage for di�erent

®xed values of the gate voltage, as simulated with the SPICE,

before and after stress.

Table 2

The SPICE sub-circuit parameters that have been adjusted so as to ®t the measurements of IRGBC20S

Type of component SPICE parameters

Name Description Unity Default values IRGBC20S values

BJT

IS Transport saturation current A 1:0� 10ÿ16 7:79� 10ÿ12

BF Ideal maximum forward beta 100 1.8

RE Emitter resistance Ohms 0 4:56� 10ÿ3

TF Ideal forward transit time ns 0 137

TR Ideal reverse transit time ns 0 646

MOSFET

VTO Zero bias threshold voltage V 0 5.1

KP Transconductance parameter A/V2 2:0� 10ÿ5 2.635

IS Bulk junction saturation current A 1:0� 10ÿ14 7:79� 10ÿ12

RS Source ohmic resistance Ohms 0 1:68� 10ÿ3

CGSO Gate source overlap capacitance per

meter channel width

F/m 0 1� 10ÿ3

PHI Surface potential V 0.6 45

LAMBDA Channel length modulation 1/V 0.0 18� 10ÿ3

GAMMA Bulk threshold parameter V1=2 0.0 5.5

A. Maouad et al. / Microelectronics Reliability 40 (2000) 973±979 977

Page 6: Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

ones before and after stress. It arises that the SPICE

parameters which had to be modi®ed are the ones re-

lated to variations in the experimental characteristics,

DC and transients. The internal static parameters of the

MOSFET (M1 in Fig. 7) which have been modi®ed are

Kp, the transconductance coe�cient and VTO, the zero-

biased threshold voltage, directly related to Vth, the

threshold voltage [7,13].

The CGD value decreases by 15% due to a variation of

the input capacitance. The variations of Kp (about 50%

decrease) yield a decrease in the carrier mobility in the

channel region, l, in the same percentage range, this

being conform to their proportional relationship [13].

The simulation shows that this SPICE sub-circuit can

take into account the DC and the dynamic characteristic

changes due to high-density-current induced defects.

5. Conclusion

These tests and analysis demonstrate the ability of

our method to simulate electrical aging under extreme

industrial operating conditions leading to functional

degradation.

The use of the SPICE sub-circuit simulation has

permitted to determine parameter values for the IGBT

after the stress.

The above method can be applied to the aging

studies. The knowledge of which, parameters are in¯u-

enced in a speci®c functional stress condition permits

to compensate for these changes or improve the

Fig. 10. Collector current versus collector voltage for a 7.0 V

®xed value of the gate voltage, as simulated with the SPICE,

before and after stress.

Fig. 11. Square root of collector current versus gate voltage for

a 5.0 V ®xed value of the collector voltage, as simulated with the

SPICE, before and after stress.

Table 3

Parameters of the SPICE sub-circuit that have changed due to

stress

Parameter Before stress After stress

Speci®c to the internal pnp transistor Q1

BF: corresponds to b in the

IGBT

1.80 1.55

TF (ns): doesnÕt correspond

to tf in the IGBT

137 145

Speci®c to the internal MOSFET transistor M1

Kp (A/V2) 2.635 1.25

VTO (V) 5.1 5.17

External to the two above transistors

CGD (nF) 17 14.5

Fig. 9. Collector current versus gate voltage for a 0.8 V ®xed

value of the collector voltage, as simulated with the SPICE,

before and after stress.

978 A. Maouad et al. / Microelectronics Reliability 40 (2000) 973±979

Page 7: Characterization of high-density current stressed IGBTs and simulation with an adapted SPICE sub-circuit

implementation of the component in a circuit, as well as

its use in the ®eld conditions.

References

[1] Baliga BJ. The insulated gate transistor, a new three-

terminal-MOS-controlled bipolar power device. IEEE

Trans Electron Dev 1984;ED-31:1790±828.

[2] Haddi A, Maouad A, Elmazria O, Ho�mann A, Charles J-P.

A simpli®ed SPICD model for IGBT. Active and Passive

Electronic Components 1998;21:279±92.

[3] Hong SH, Nam SM, Yun BO, Lee BJ, Yu CG, Park JT.

Temperature dependence of hot carrier induced MOSFET

degradation at low gate bias. Microelectron Reliab

1999;39:809±14.

[4] Wondrak W. Physical limits and lifetime limitations of

semiconductor devices at high temperatures. Microelectron

Reliab 1999;39:1113±20.

[5] Dreesen R, Croes K, Manca J, De Ceuninck W, De

Schepper L, Pergoot A, Groeseneken G. Modelling hot-

carrier degradation of LDD NMOSFETs by using a high-

resolution measurement technique. Microelectron Reliab

1999;39:785±90.

[6] Hefner AR. An analytical model for the steady-state and

transient-characteristics of the power IGBT. Solid State

Electron 1988;31(10):1513.

[7] Silvaco International, SmartSpice/UTMOST III Modeling,

User Manual, Santa Clara, 1995.

[8] Mitter CS, Hefner AR, Chen DY, Lee FC. Insulated gate

bipolar transistor (IGBT) modeling using IG-SPICE. IEEE

Trans Industry Appl 1993;30(1):24±33.

[9] Charlot J-J, Pesic I. Spice and user developed modeling

application: implementation of an IGBT model in smart-

spice. Simulation Silvaco, 1994.

[10] Liu C-M, Kuo JB. Turn-o� transient analysis of a double

di�used metal-oxide-semiconductor device considering

quasi-saturation. J Appl Phys 1995;34(2B).

[11] Elmazria O. Caracterisation et simulation de lÕIGBT dans

le but dÕoptimiser ses performamces au moyen de lÕirradi-

ation par electrons. Ph.D. Thesis, Metz University, 1996.

p. 120.

[12] Messenger GC, Ash MS. The e�ects of radiation on

electronic systems. New York: Van Nostrand Reinhold,

1986.

[13] Pizano JE, Ma TH, Attia JO, Schrimpf RD, Galloway KF,

Witulski AF. Total dose e�ects on power-MOSFET

switching converters. Microelectron Reliab 1998;38:

1935±9.

A. Maouad et al. / Microelectronics Reliability 40 (2000) 973±979 979