Discrete-time Decimation filter Design for Multistandard RF Sub-sampling Receiver

Rim Barrak, Adel Ghazel CIRTA’COM Laboratory

Ecole Supérieure des Communications Cité technologique des Communications,Tunis, Tunisia rim.barrak@supcom.rnu.tn, adel.ghazel@supcom.rnu.tn

Fadhel Ghannouchi Intelligent RF Radio Laboratory

The University of Calgary Calgary, Canada

fghannou@ucalgary.ca

Abstract—Sampling-based downconversion architecture was proposed in [1] for multistandard RF subsampling receiver. By an appropriate choice of RF and IF subsampling frequencies complete multistandard RF bands are downconverted to baseband. This paper presents a reconfigurable discrete-time switched capacitor filter at the baseband stage which serves as an anti-aliasing and a decimation filter for Analogue to Digital Converter. The proposed decimation filter structure consists of two cascaded second order decimation filters which are adapted respectively for GSM, UMTS and IEEE-802.11g multistandard radio receiver. The overall transfer function of this structure can be changed by switching the received channel path and adjusting the clock signal frequency controlling the switched-capacitors. IIR and FIR filter switched-capacitor implementations are also investigated to evaluate designed filter complexity and performance.

I. INTRODUCTION A tremendous growth in the wireless communication

market has been announced in the last years. Some research activities have been carried to define RF system receiver architectures that can support various standards [2-4] with multimode operation, low cost, reduced size and increased battery life of user equipment hardware. According to software radio objectives, multistandard receiver hardware has to be reconfigured by software with maximum hardware functionality sharing between various standards.

Some RF subsampling receivers have been proposed for GSM [5], 802.11b [6] and Bluetooth [7]. The corresponding receiver topologies are based on switched-capacitor (SC) circuits to perform discrete-time processing after sampling. This leads to an excellent improvement for radio receiver performances, integration and low power dissipation. However, designed RF front-end receivers are optimized only for a single standard. Recently, a new sampling-based downconersion topology for multistandard receiver was proposed [1]. The proposed architecture achieves multiple RF bands downconversion to IF domain by RF subsampling. Then, desired channel downconversion to baseband is obtained by IF subsampling. According to this topology, significant design advantages at RF system level architecture are

obtained compared to other proposed RF sampling architectures.

The objective of this research contribution is to design a reconfigurable discrete-time decimation filter placed after IF subsampling stage in order to relax constraints on ADC in terms of dynamic range and sampling rate and ensure required configurability for multimode operation in multi-standard radio receiver with high-level integration.

This paper is organized as follows. In section II multistandard RF subsampling receiver is reviewed and discrete-time decimation filter general specifications are presented. According to GSM, UMTS and 802.11g RF subsampling receiver design specifications [2-4], proposed reconfigurable decimation filter structure is presented in section III. Finally, IIR and FIR filter implementations are discussed in section IV for design complexity and performance evaluations.

II. MULTISTANDARD RF SUBSAMPLING RECEIVER

The proposed RF subsampling multistandard receiver architecture is shown in figure 1. This architecture is composed by a first tuned RF filter, a wideband low noise amplifier (LNA), a second tuned RF filter, a first track and hold circuit (T&H), an IF filter, a second quadrature T&H followed by decimation filter and an analog to digital converters (ADC).

ADC DSP

fs

Tunning selected channels

I

QAGC

AGC

f 'sn90°

DecimationFilter

T&H1

T&H2

f 'sn/MM

M

RF Stage IF Stage BB Stage

MultibandRF Filter 1

WidebandLNA

WidebandAntenna

MultibandRF Filter 2 IF Filter

Tunning RF bands

Figure 1. Multistandard RF subsampling receiver architecture

The first wide-band T&H1 with fixed RF subsampling frequency clock (fs), samples the output of analogue RF front-end, and, thereby downconverts the multistandard RF bands to the same intermediate frequency band located in [0 fs/2]. To

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relax requirements on ADC in terms of bandwidth and sampling rate, a second T&H circuit with tunable IF frequencies clock (f'sn) performs desired channel quadrature downconversion to baseband. An RF bandpass filter, placed before T&H1, is needed before RF sampling to perform anti-aliasing [8]. As well, an IF bandpass filter is needed before second T&H2 [9]. After T&H2 circuit a discrete time low-pass decimation filter followed by an Automatic Gain Control (AGC) are proposed to further reduce dynamic range and sampling rate at the ADC input.

For analog to digital conversion, we choose a Σ∆ modulator because it is well used for multistandard applications due to its adaptability and programmability. Sampling rate decimation order has to be adjusted for each standard specification, in order to meet required ADC dynamic range and sampling rate. A low pass filter is needed before decimation. Switched capacitor filter implementation performs discrete-time processing and therefore provides multistandard capabilities to the system.

GSM, UMTS and 802.11g standards are chosen as a target for the radio receiver design. RF and IF stages of figure 1 have been designed in [1]. The objective of this contribution is to design baseband stage, spatially, the decimation filter block which depends on ADC sampling rate performance.

III. DECIMATION FILTER DESIGN

In this section, ADC specifications will be presented in order to derive decimation order requirement. Then, the architecture and the specifications of decimation filter blocks will be provided.

A. Analog to Digital Converter requirements From multistandard ADC state-of-the-art solutions, a

reconfigurable Σ∆ modulator is chosen as a trade-off between sampling rate and dynamic range. This multimode ADC was designed for a GSM/WCDMA/WLAN/WiMAX zero-IF receiver [10].

In GSM mode, the designed ADC can achieve a dynamic range of 83dB when sampling at 32 MHz. The dynamic ranges and sampling rates can reach 75 dB, 64 MHz and 62 dB, 160 MHz respectively for WCDMA and WLAN/WiMAX modes.

In the multistandard RF subsampling architecture, all RF channels are downconverted to baseband at IF stage output. Hence, the selected ADC can be easily adapted for GSM/UMTS/802.11g RF subsampling receiver architecture.

B. Decimation filter blocks By considering GSM, UMTS and 802.11g standards

specifications, a first subsampling frequency clock of 761.8 MHz was chosen to down convert different RF

bands to the same IF band [114.6 MHz 198.2 MHz], to optimize RF and IF filters design and to reduce first T&H noise due to aperture jitter and subsampling thermal noise [1]. A second T&H circuit with tunable IF clock frequencies is proposed to perform desired channel quadrature downconversion to baseband.

Table I summarizes the RF subsampling receiver frequency plan for GSM, UMTS and 802.11g standards.

TABLE I. FREQUENCY PLAN FOR GSM/UMTS/802.11G RECEIVER

GSM UMTS 802.11g RF Bands (MHz) 925-960 2110-2170 2400-2483.5 fs (MHz) 761.8 IF bands (MHz) 163.2-198.2 115.4-175.4 114.6-198.1

f'sn (MHz) 163.4-198 (step = 0.2)

117.8-173 (step = 0.2)

126.6-186.6 (step =5)

According to multistandard ADC sampling rates

requirement presented in section A and IF sampling rates, a discrete-time decimation stage between T&H2 and ADC is proposed. Decimation order (M) has to be adapted to the selected radio standard. We choose M=4, M=2 and M=1 respectively for GSM, UMTS and 802.11g.

The decimation filter can be configured in two cascaded second order decimations; each one is preceded by a low pass filter that provides the optimal performance for different standards. For some standards, the unused blocks will be switched off, resulting in large power savings. Proposed multimode decimation filter structure is described by figure 2. This is architecturally and parametrically configurable for power optimization in relation to the selected radio standard.

2 2 ADCGSM

UMTS

802.11gAGC

GSM

UMTS

Digital command

fs802.11g

fs/4

fs/2

LPF LPF

Figure 2. Multimode decimation filter

C. Decimating filters specifications IF subsampling frequency (f'sn) is tuned according to

selected standard channel. Due to decimation by M, a number of image frequencies can alias into the baseband. These frequencies are expressed by:

fimage=i*f'sn/M, i=1,…, M-1 (1)

Let's Fc and Fr be the lowpass filter cut-off and rejection frequencies normalized by half minimum IF sampling frequency (f'smin/2). Fc and Fr are given by equations 2 and 3.

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2'f2

B

Fmins

ch

c = (2)

2'f

2B

M'f

Fmins

chmins

r

−=

(3) Where Bch is selected channel bandwidth.

Decimation filter attenuation is calculated from blockers or interferers located at image frequencies. Decimation filter mask associated to minimum sampling frequency is given by figure 3.a. Increasing sampling frequency which controls discrete time decimation filter will change filter response normalized by f’smax/2 (see figure 3.b) in order to be adjusted to the required band selection and attenuation. Hence, in order to derive the specifications of first and second low pass decimation filters in figure 2, the minimum IF sampling frequency has to be considered.

10.5

Att

Fc 2f/f’smin

Response(dB)

Decimation filter masknormalized by f’smin

Fr

0

10.5F’c2f/f’smaxF’rFc

Fr

Response(dB)

Decimation filter masknormalized by f’smax

Att

(a) (b)

Figure 3. Decimation filter mask

The first low pass filter in figure 2 is shared by GSM, UMTS and 802.11g standards. Filter selection band has to be greater than half 802.11g channel bandwidth (11MHz). GSM and UMTS rejection frequencies are located respectively at Fr_GSM and Fr_UMTS which are calculated from equation 3 where M =2. Required attenuations are 85 dB for GSM and 51.8 dB for UMTS. For 802.11g mode, selected channel will not be decimated; therefore, there is no need to attenuate any image signals. However, first filter response contributes in 802.11g dynamic range improvement.

First decimation filter mask is given by figure 4. The proposed filter presents maximum functionality sharing between the three standards.

10.5

AGSM

AUMTS

Fc_GSM 2f/fs

Response (dB)First filter mask

UMTS maskGSM mask

Fc_UMTS Fc_802.11g Fr_GSMFr_GSM

Figure 4. First decimation filter mask

The second low-pass filter in figure 2 is designed for GSM mode. His mask is given by figure 5. Cut-off

frequency and rejection frequency are calculated respectively from equations 2 and 3 where M=4.

10.5

AGSM

F’c_GSM 4f/fs

Response (dB)Second filter mask

F’r_GSM Figure 5. Second decimation filter mask

IV. DISCRETE-TIME FILTER IMPELEMENTATION

A. Filter structure issue In order to evaluate design complexity and performance,

Finite Impulse (FIR) and Infinite Impulse (IIR) responses that respect decimation filters masks have been investigated.

IIR and FIR filter responses have been synthesized using Mathlab filter Design and Analysis Tool. The selection criterions are: stability, order, phase-linearity, out-band attenuation and switched-capacitor implementation complexity. Nuhertz filter 2006 tool was used to achieve filter circuit schematic based on discrete-time implementation .

For an appropriate out-band attenuation, filter stability and phase-linearity are always ensured for FIR responses, whereas they have to be verified for IIR responses. For example, for the first filter design, Chebyshev IIR and Hamming FIR responses which have respectively 2nd and 9th orders respect defined filter specifications. These responses are also stable and verify phase linearity. The associated circuit implementations present a capacitive area of 30 Cunit and 75 Cunit respectively for IIR and FIR structures. Cunit corresponds to the lowest capacitance value which depends on CMOS implementation technology.

An Infinite Impulse chebyshev response was selected to realize the two low-pass decimation filters. In such application, IIR structure presents the lowest complexity implementation with an appropriate design performance.

B. First filter implementation The designed IIR first decimation filter transfer function is

given by equation 4.

2-1-

21

Z0.559Z1.311-1ZZ21

0.055)Z(H+++

=−−

(4)

This corresponds to a second order chebyshev response. The circuit discrete-time implementation method is based on switched-capacitor Biquad architecture [11]. First filter circuit schematic is shown in figure 6 along with the appropriate clock scheme (Φ1 and Φ2). Φ3 clock scheme realizes second order decimation for GSM and UMTS modes. Ts is IF sampling frequency inverse. Capacitances values were optimized to minimize capacitance spread between Cmin and Cmax and minimize

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global size circuit [11]. We found C1=Cunit, C2=1.12Cunit, C3=6.74Cunit, C4=7.98Cunit, C’1=Cunit, CA=1.68Cunit and CB=10.12Cunit. This corresponds to capacitance area of 29.64Cunit.

φ1

φ1φ1 φ1

φ1

φ2φ2

φ2

φ2

φ2

C2

C4

CA

C1 C3

CB

C5

+

-

+

-

A1A2

φ3

φ2

UMTS/GSM

802.11g

φ2

φ1

Ts

φ3

Figure 6. The circuit schematic of first IIR filter

C. Second filter implementation The designed IIR second decimation filter transfer

function is given by equation 5. This corresponds to a first order chebyshev response.

1-

1

Z0.892-1Z1

0.054)Z(H−+

= (5)

Second filter circuit schematic is shown in figure 7 along with the appropriate clock scheme (Φ1 and Φ2). Φ3 clock scheme realizes second order decimation for GSM mode. We found CS=CD=Cunit and CE=8.33Cunit. This corresponds to capacitance area of 10.83Cunit.

φ1φ2

φ1

φ2φ1

φ2

CD

CE

CS

+

-

A3φ3

GSM

φ2

φ1

Ts/2

φ3

φ2

CS/2

φ2

UMTS

Figure 7. The circuit schematic of second IIR filter

According to designed decimation filter responses, the maximum blockers level at filter output and required AGC gain variation have been calculated respectively for GSM,

UMTS and 802.11g standards. This can reduce required multimode ADC dynamic ranges. Table II gives ADC dynamic range specifications with and without gain control. The resulting ADC dynamic ranges meet multimode ADC requirements given in section III. The last result accomplishes multistandard RF subsampling receiver specifications design.

TABLE II. AGC AND ADC REQUIREMENTS

GSM UMTS 802.11gDRADC without AGC (dB) 96 73.8 70∆GAGC (dB) 15.2 25.7 30.7DRADC with AGC (dB) 80.8 48.1 39.3

V. CONCLUSION A reconfigurable discrete-time decimation filter is proposed

for baseband stage in RF subsampling multistandard radio receiver. Decimation operation is realized in two cascaded second order decimation preceded by low-pass filter in order to achieve multimode operation. Decimation filters masks are derived from GSM, UMTS and 802.11g standards specifications. This leads to second order chebyshev IIR response followed by first order chebyshev reponse. The overall structure presents the lowest complexity implementation with an appropriate design performance.

REFERENCES [1] R. Barrak, A. Ghazel, F. M. Ghannouchi, "Optimized multistandard RF

subsampling radio receiver design", submitted to IEEE transactions on Wireless Communication, Jan. 2007.

[2] Radio Transmission and Reception GSM 05.05. ETSI, 1996. [3] UMTS UE. Radio Transmission and Reception (FDD), 3GPP TS25.101

Version 5.2.0 Release 5 ETSI 2002. [4] [Part 11: Wireless LAN Medium Access Control (MAC) and Physical

Layer (PHY) specifications, Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, IEEE Std 802.11g™-2003.

[5] K. Muhammad et. al., "Digital RF processing: Toward low-cost reconfigurable radio", IEEE Communications Magazine, PP. 105- 113, Aug. 2005.

[6] Jakonis, D.; Folkesson, K.; Dabrowski, J.; Eriksson, P.; Svensson, C.;"A 2.4-GHz RF Sampling Receiver Front-End in 0.18um CMOS", IEEE Journal of Solid-State Circuits, Volume 40, Issue 6, PP. 1265-1277, June 2005.

[7] K. Muhammad et. al., "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS", IEEE Journal of Solid-State Circuits, Volume 39, Issue 12, PP. 2278-2291, Dec. 2004.

[8] R. Barrak, A. Ghazel, F. M. Ghannouchi, "Design and Optimisation of RF Filters for Multistandard RF Sub-sampling Receiver", IEEE International Conference on Design and Test of Integrated Systems in Nanoscale technology, Sept. 2006.

[9] R. Barrak, A. Ghazel, F. M. Ghannouchi, "Design of Sampling-Based Downconversion Stage for Multistandard RF Subsampling Receiver", 13th IEEE International Conference on Electronics, Circuits and Systems, Dec. 2006.

[10] A. Rusu, et al. "Reconfigurable ADCs enable smart radios for 4G wireless connectivity", IEEE Magazine Circuits and Devices, Vol. 22, No. 3, May-June 2006, PP. 6 – 11.

[11] R. Gregorian and G. C. Temes, "Analog MOS Integrated Circuits for Signal Processing" New York, NY: Wiley, 1986.

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