Examination of Punch-Through Insulated Gate Bipolar Transistors Under Positive and Negative

Gate Bias Stress

C. O. Maïga, B. Tala-Ighil, H. Toutah and B. Boudart

Laboratoire Universitaire des Sciences Appliquées de Cherbourg Ecole d’Ingénieurs de Cherbourg,

B.P.78, Rue Louis Aragon, 50130 Cherbourg-Octeville, France.

Abstract - The work presented in this paper is concerned

with the effects of a positive and of a negative gate bias

stress on Punch-Through Insulated Gate Bipolar

Transistors (PT-IGBT’s). Two selections of PT IGBT’s all of

the same nominal range were gate biased at their positive

and negative maximum gate-to-emitter voltage with drain

and emitter short-circuited at 140°C during 1200 hours. A

particular interest was taken in the switching parameters.

Experimental results on their evolution under the two types

of stress are presented in a quantified way. Then, a

qualitative analysis of the effects of the switching times shift,

due to the IGBT’s ageing, on a PWM inverter operation is

presented.

I. INTRODUCTION

The semiconductor component is the key element in the reliability and the safety operation of static power converters. A lot of failures are directly correlated to it. During their lifetime, these components are subjected to various constraints such as the dv/dt, di/dt, presence of collector-to-emitter voltage, gate polarisation… These constraints can, in the long - term, lead to the modification of some of their characteristics. This modification could have destructive consequences on the converter. Today, the IGBT’s are the most widely used semiconductor power devices in the mid-power range. They are used because of their attractive characteristics such as low on-state voltage drop and switching frequencies up to, and even more than, 20 kHz [1]. Since a few years, in its discrete or module form, it has become also a device of the highest importance in the high power converters. Various structures were proposed to improve the performances of the device. But, the must widely used IGBT structure today in the 600-1200 V range is the Punch-Through (PT) structure [1], [2], [3]. However, the phenomenon of ageing of the IGBT’s has formed the subject of only few investigations essentially due to the complexity of their internal structure and the multiplicity of involved phenomena. Some recent and interesting studies have been published on this problem over the last years [4], [5], [6]. Nevertheless, these studies did not take into account the device technology and were not interested in the various parameters linked to the switching mode operation. These parameters are of great importance for devices intended to be used in a static power converter; and that is why a large and systematic examination of the ageing of different structures of this

device under various electric stresses is undertaken [7], [8]. We present in this paper a quantified and compared study of effects of a positive and a negative gate bias stress on PT IGBT’s. Experimental results on the evolution of the parameters related to the switching mode operation are presented in a quantified way and a qualitative analysis of the effects of the switching times shift, due to the IGBT’s ageing, on a PWM inverter operation is presented. The aim is, in the long term, to constitute a database as complete as possible for the analysis and diagnosis of failure causes, related to the switching devices, in a power conversion systems.

II. DEVICE STRUCTURE

The structure of Punch-Trough IGBT is illustrated by the schematic cross section of Fig. 1. The device parameters which influence the characteristics of PT IGBT’s are well known [3] and have been incorporated by almost all commercial IGBT manufacturers [1]. The Punch-Trough IGBT has the same structure as Power MOSFET except the N+ drain which is replaced by a strongly doped P+ layer.

Collector

P+

MOSFET channel Gate

Emitter

N+ N+

P P

P+

Substrate P+P+

Buffer layerN+

N-

Gate oxide

Drift region

Fig. 1. PT IGBT structure

IEEE ISIE 2005, June 20-23, 2005, Dubrovnik, Croatia

0-7803-8738-4/05/$20.00 ©2005 IEEE 435

The P+N- junction thus formed injects holes in the vital region N-, so it is possible to modulate its resistivity with the channel electrons [9]. The vital region N- is carried out by epitaxy dumping. The substrate is P+ type. The manufacturers introduce a thin N+ buffer layer between the P+ substrate and the vital region N- to control the carriers flow [10]. Thanks to the presence of the buffer layer in the PT structure, the evacuation of the stored charges in the base of IGBT's is easier. It’s done by recombination in the N-/N+ interface region. It permits to minimise the current tail at turn-off. The latch-up phenomenon is less important and the IGBT's are faster in switching applications [9], [10]. In this technology, it is possible to adjust the carriers injection efficacy to have a weak on-state voltage drop [11]. The reverse blocking voltage is determined by the P+ substrate and N+ buffer layer. Therefore, an increase of the buffer layer thickness induces a reduction of the IGBT blocking voltage. Due to a low emitter injection efficacy of the PT IGBT's, the fall time and the current tail are short [7]. With a buffer layer, PT-IGBT is optimised to support a positive blocking voltage but the static performances of IGBT are decreased by reduction of injection efficacy [9]. To avoid the drilling of the bipolar transistor, the region of space charge should not be spread out over all the drift region.

III. EXPERIMENTS

Commercially-available IRG4BC20F IGBT's from International Rectifier were used in this study. The IRG4BC20F is rated at a collector current of 16 A @ 25°C with a reverse blocking voltage of 600 V. Two selections of transistors were constituted. The First selection was gate biased at its maximum positive gate voltage V20VGE += while the second one was gate

biased at its maximum negative gate voltage V20VGE −= . In the two cases, the collector and the

emitter were short-circuited and, to accelerate the phenomena of ageing, the stress was carried out at 140°C, just under the maximum junction

temperature C150Tj °= .

IV. SWITCHING TEST CIRCUIT AND INSTRUMENTATION

To measure the various switching parameters, a series chopper flowing in an inductive load, as encountered in most applications, was used. After each duration of stress, the transistors were introduced into the test circuit shown in Fig. 2. The device under test (DUT) was paralleled with an identical and not stressed IGBT called “Pilot Device”. A driver circuit delivers a series of adjustable frequency and duty cycle pulses. One on 1024 pulses is inhibited on the gate of the pilot device and switched to the gate of the DUT. While the pilot device is switched at a frequency of 2 kHz, the DUT is only approximately switched at 2 Hz : it is requested only during 200 µs every 500 ms. This frequency was chosen to avoid the heating of the device under measurements. The room temperature was 25°C. This measuring mode allows the use of the averaging function of the oscilloscope if required. This is why it was preferred to the single-shot operating mode. The gate resistor GR

was deliberately chosen of a high value to accentuate some phenomena such as the stage of "Miller effect" on the gate voltage.

DUTGateDrive

Circuit

GateDriveCircuit

RG RG

Pilote

Load DF

E

DUT drivepulses

Pilot Devicedrive pulses

Dri

ve

vo

ltag

e v

D

Gat

e vo

ltag

e v

G

Co

llec

tor

curr

ent

i C

Collector-

voltage vCE

to-Emitter

Device

Fig. 2. Switching test circuit

In order to correctly apprehend the switching parameters, no snubber circuit has been used. The various switching times, the on-state voltage drop and the switching losses were measured using a TEKTRONIX oscilloscope model TDS754D in association with TEKTRONIX voltage probes model TEK P6139A and a current probe model TCP202. The switching times were obtained in the usual way : the rise time was computed from 10% to 90% of the final current, the fall time from 90% to 10% of the final current, the turn-on delay time from 10% of the gate voltage to 10% of the final current and the turn-off delay time from 90% of the gate voltage to 90% of the final current. The turn-on losses were measured from the beginning of the collector current increasing to the end of stage of “Miller effect” on the gate voltage, when the collector-to-emitter voltage reaches its on-state value. The turn-off losses were computed from the beginning of the collector-to-emitter voltage increasing to about 1% of the collector current.

V. RESULTS AND DISCUSSION

A. Gate threshold voltage

The gate threshold voltage )th(GEV is defined as the

value of the voltage on the gate GEV corresponding to

collector current A250IC µ= with GECE VV = [12]. It

was measured at a constant temperature of 30°C. Fig. 3

shows the shift 0),th(GEs),th(GE)th(GE VVV −=∆ of this

parameter where 0),th(GEV is the initial value of )th(GEV

before stress and s),th(GEV is )th(GEV value for each

stress time. The gate threshold voltage increases for the positive gate bias stress while it decreases, and more significantly, for the negative gate bias stress during the first hundreds hours of stress, then saturates and remains unchanged in the two cases.

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0 240 480 720 960 1200

-750

-600

-450

-300

-150

0

150

300

450

VGE

=+20 V, VCE

=0

VGE

=-20 V, VCE

=0

Thre

shold

volt

age

shif

t ∆V

GE

(th) (

mV

)

Stress Time (hours)

Fig. 3. Threshold voltage shift versus stress time

The threshold voltage evolution can be explained by trapped charges located in the oxide and/or at the oxide-semiconductor interface and/or by mobile charges in the gate oxide. This process being cumulative, it induces the increase or the decrease of the threshold voltage [4], [13]. However, the negative gate bias stress involves a more important threshold voltage shift than the positive one.

B. Gate-emitter leakage current

The gate-emitter leakage current was measured after each stress duration at a constant temperature of 30°C with a gate-to-emitter voltage V20VGE = and collector-

emitter short-circuited. Fig. 4 displays its variation

0,GESs,GESGES III −=∆ as a function of the stress time

where 0,GESI and s,GESI are the initial value of GESI

before stress and its value for each stress time, respectively. It allows highlighting a strong increase for the positive gate bias stress. This current was not measured for the negative gate bias stress.

0 240 480 720 960 12000,0

0,5

1,0

1,5

2,0

VGE

=+20 V, VCE

=0

Gat

e-em

itte

r le

akag

e cu

rren

t sh

ift

∆IG

ES (

pA

)

Stress Time (hours)

Fig. 4. Gate-emitter leakage current shift versus stress time

C. Zero gate voltage collector current

The zero gate voltage collector current CESI was also

measured at a constant temperature of 30°C with collector-to-emitter voltage V600VV CEMAXCE ==and gate-to-emitter short-circuited. Its shift

0,CESs,CESCES III −=∆ is shown in Fig. 5. It increases

during the first hundreds hours of the stress, then saturates and remains unchanged as well as for the positive than for the negative gate bias. The shift is more important in the case of positive gate bias.

D. On-state voltage drop

The on-state voltage drop )on(CEV is the key rating to

calculate the conduction losses. It was measured for a collector current of A10IC = . Its shift variation

0),on(CEs),on(CE)on(CE VVV −=∆ versus stress time is

shown in Fig. 6. 0),on(CEV is the initial value of )on(CEV

before stress and s),on(CEV is its value for each stress

time. The on-state voltage drop increases strongly and practically in the same proportions for the two gate bias stresses.

The presence of the N+ buffer layer in the PT structure ensures a lower initial value of the on-state voltage drop but involves more variation during the stress because of its high temperature sensitivity [7], [10], [13]. In PT-IGBT submitted at the high temperature gate bias stress, the electric field in the drift region involves a more important degradation of carriers mobility, which induces an increasing of N- channel resistance and consequently an increase of on-state voltage drop [7], [10].

0 240 480 720 960 12000

200

400

600

800

VGE

=+20 V, VCE

=0

VGE

=-20 V, VCE

=0

Zer

o g

ate

volt

age

coll

ecto

r cu

rren

t sh

ift

∆IC

ES (

nA

)

Stress Time (hours)

Fig. 5. Zero gate voltage collector current shift versus stress time

0 240 480 720 960 12000

25

50

75

100

125

150

VGE

=+20 V, VCE

=0

VGE

=-20 V, VCE

=0

On-s

tate

volt

age

dro

p s

hif

t ∆V

CE

on (m

V)

Stress Time (hours)

Fig. 6. On-state voltage drop shift versus stress time

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E. Turn-on delay time and rise time

The variation of turn-on delay time and of rise time of the collector current are illustrated in Fig. 7.They are

respectively defined as 0,dons,dondon ttt −=∆ and

0,rs,rr ttt −=∆ , where 0,dont and 0,rt are the initial

values of dont and of rt before stress; s,dont and s,rt

are their values for each stress time. The turn-on delay time increases by 25% for the positive gate bias while it decreases almost in the same proportions in the case of negative gate bias after 1200 hours of stress. The evolution of the turn-on delay time can be directly related to the evolution of the gate threshold voltage. The trapping of carriers at the interface gate oxide/semiconductor is more enhanced when the gate is submitted to positive bias, so the threshold voltage involves and consequently the turn on delay time increases. This process is reversed in the case of negative bias is applied on the gate. [4], [14].

The rise time increases for the two types of stresses but in a more significant manner in the case of negative gate bias stress. The shift of these parameters continues after 1200 hours of stress.

F. Turn-off delay time and fall time

The behaviour of the turn-off delay and the fall time are shown on Fig. 8. These parameters are defined as

0,doffs,doffdoff ttt −= and 0,fs,ff ttt −= ,

respectively where 0,dofft and 0,ft are the initial values

of dofft and of ft before stress; s,dofft and s,ft are

their values for each stress time. The turn- off delay time and the fall time decrease as well as for the positive than for the negative gate bias stress but noticeably in a more significant manner for the positive one. The shift continues after 1200 hours of stress.

During the turn-off time, the reduction of the gate voltage causes a decreasing of the channel current (electron current). Thus, there are less stored carriers and consequently the turn-off delay time decreases during the stress. This parameter strongly depends on the gate charge [7], [15].

G. Switching losses

The evolutions of the Turn-on losses onW and the

Turn-off losses offW versus stress time are shown in

Fig. 9. They are defined as 0,ons,onon WWW −=∆ and

0,offs,offoff WWW −=∆ , where 0,onW and 0,offW are

the initial values of onW and of offW before stress,

respectively. s,onW and s,offW are their values for each

stress time.

The turn-on and the turn-off losses increase as well as for the positive than for the negative gate bias stress but more significantly for the last case. The positive variation of the turn-on losses is due to the continuous increase of the collector current rise time during these stresses. The turn-off losses increase in spite of the switching-off times decrease. This could be explained by the increase of the collector voltage rise time during these stresses.

0 240 480 720 960 1200

-150

-100

-50

0

50

100

150

∆tdon

: VGE

=+20 V

∆tdon

: VGE

=-20 V

Turn

-on d

elay

tim

e sh

ift

∆tdo

n (n

s)

Stress Time (hours)

0

10

20

30

40

50

60

Ris

e ti

me

shif

t ∆t

r (ns)

∆tr : V

GE=+20 V

∆tr : V

GE=-20 V

Fig. 7. Turn-on delay time and rise time shifts versus stress time

0 240 480 720 960 1200

-120

-100

-80

-60

-40

-20

0

∆tdoff

: VGE

=+20 V

∆tdoff

: VGE

=-20 VTurn

-off

del

ay t

ime

shif

t ∆t

doff (

ns)

Stress Time (hours)

-75

-60

-45

-30

-15

0

Fal

l ti

me

shif

t ∆t

f (ns)

∆tf : V

GE=+20 V

∆tf : V

GE=-20 V

Fig. 8. Turn-off delay time and fall time shifts versus stress time

0 240 480 720 960 12000

10

20

30

40

50

60

70 ∆Won

: VGE

=+20 V

∆Won

: VGE

=-20 V

Turn

-on l

osse

s sh

ift

∆Won (µ

J)

Stress Time (hours)

0

5

10

15

20

25

30

35

Turn

-off

loss

es s

hif

t ∆W

off (

µJ)

∆Woff

: VGE

=+20 V

∆Woff

: VGE

=-20 V

Fig. 9. Switching losses shift versus stress time

VI. EFFECTS OF THE SWITCHNIG TIMES DEGRADATION ON

PWM INVERTER OPERATION

A. Dead Time Effects

In recent years considerable efforts have been devoted to improving the performance of PWM inverters in both the theoretical aspects and the implementation of the control circuits. As a result, versatile PWM techniques are now available and in use for various applications.

As any semiconductor-switching device, the IGBT's react delayed to the turn-off signals owing to the storage time. During this storage time, depending on the operating point, the switch is not able to block the DC link voltage. Therefore, to avoid a short circuit of the

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half-bridge, a dead time interval must be introduced between the turn-off signal of a transistor and the turn-on signal controlling the opposite transistor. The dead time

dτ is usually constant and determined as the value of the

turn-off time offt plus an additional safety margin. The

dead times of common IGBT inverters used in industry vary between sµ1 to sµ5 .

The effects of the dead time on the output voltage are well known and will be described from one half-bridge of three-phase PWM inverter according to Fig. 10. The gate drive signals 1G and 2G for the transistors 1T and 2T

respectively are illustrated in Fig. 11-a where the rising edges of the drive signals are delayed by the dead time

dτ from the ideal signals. During the dead time, the

output terminal “A” seems to be floating. However, the output current i(t) being continuous, it flows through one of the freewheeling diodes 1D or 2D . When 0)t(i > ,

the diode 2D conducts and negative voltage appears at

the output terminal. For the current 0<)t(i a positive

voltage appears at the output through 1D . As a result, the

output voltage )t(u 0A deviates from the ideal PWM

waveform as indicated by the grey marked areas in Fig. 11-b and Fig. 11-c.

With a positive current, the duty cycles are shorter and with negative current longer than required. Hence, the actual duty cycle is always different from the one of the reference voltage. It is either increased or decreased, depending on the load current polarity. As a natural consequence, the fundamental component decreases and there appear the undesired fifth and seventh-order harmonics in the output voltage which cause overall distortion of the inverter output waveforms [16].

B. Switching Times Effects

The waveforms presented in Fig. 11-b and Fig. 11-c are based on the assumption that the IGBT's switch on or off exactly at the instants the control signal dictates. In reality, the IGBT's present a turn-on time rdonon ttt +≈and a turn-off time fdoffoff ttt +≈ . Fig. 11-d and

Fig. 11-e show the waveforms of the output voltage when these switching times are taken into account. In this representation, it is admitted that : At the turning-on, a transistor is considered ON only when its collector current reaches its final value and its collector voltage

CEv begins to decrease. At the turning-off, a transistor is

considered OFF only when its collector voltage reaches its final value and its collector current CI begins to

decrease. The fall times of collector voltage CEv and

collector current CI are neglected. As a consequence,

when 0)t(i > , the output voltage remains at 2/E-

during the turn-on time ont of 1T and at 2/E+approximately during its turn-off delay time dofft . When

0)t(i < , the output voltage remains positive during the

turn-on time ont of 2T and negative approximately

during its turn-off delay time dofft .

E/2

E/2

TimeDead

T1

T2

D1

D2

PWMsignal

0 A

G2G1

i(t)

uA0(t)

Fig.10 . Single Phase Configuration of PWM inverter

τd

τd

uao

for i>0

E/2

-E/2

E/2

-E/2

uao

for i<0

E/2

-E/2

E/2

-E/2

τd τd

toff

0

0

0

0

uao

for i>0

uao

for i<0

G1

G2

(a)

(b)

(c)

(d)

(e)

ton

τdton

τdton

Fig.11 Output voltage waveforms

When a positive voltage is applied on the gate, the turn-on time increases whereas the turn-off time decreases. So, during this stress, as indicated by the hachured areas in Fig. 11-d and Fig. 11-e, the positive pulse duration of the output voltage will be shortened

when 0)t(i > or lengthened when 0)t(i < . Thus, the

output voltage deviation due to the dead time dτ will be

accentuated in the time for PT- IGBT submitted to the positive High Temperature Gate Bias stress.

On the other hand, when a negative voltage is applied on the gate, the turn-off time decreases and the turn on time also decreases in spite of the rise time increase. The hachured areas in Fig. 11-d and Fig. 11-e will be shortened. The waveform of the output voltage will tend to the one provided with dead time (Fig. 11-b and Fig. 11-c).

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VII. CONCLUSION

The obtained results within this study provides some interesting information on the behaviour of Punch-Through IGBT’s submitted to positive and to negative High Temperature Gate Bias stresses. These information are particularly interesting with regard to switching mode operating of these devices. The variation of the important parameters of Punch-Through IGBT structure has been highlighted : the zero gate voltage collector current, the gate-emitter leakage current, the on-state voltage drop, the rise time, the turn-on and the turn-off losses increase while the turn-off delay time and the fall time decrease as well as for the positive than for the negative gate bias. The gate threshold voltage and the turn-on delay time increase for the positive gate bias and decrease for the negative one. The consequences of the IGBT's ageing on PWM inverter operation were examined. For a positive gate bias stress, the degradation of the switching times accentuates the dead time effects in PWM inverters particularly in the case of a high frequency modulation. In the case of negative gate bias stress the additional deviation due to the switching times would be attenuated in the time. An analytic study of this problem could constitute an interesting future step for this work.

ACKNOWLEDGEMENT

This work has been carried out with the financial help of the European Community (FEDER)

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