phys. stat. sol. (c) 4, No. 6, 2175–2179 (2007) / DOI 10.1002/pssc.200674416

© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Innovative electrochemical deep etching technique involving

aluminum thermomigration

S. Kouassi*, 1, 3, G. Gautier**, 2, L. Ventura2, J. Semai2, C. Boulmer-Leborgne3, B. Morillon3,

and M. Roy3

1 Groupe de Recherche sur l’Energétique des Milieux Ionisés (GREMI), University of Orléans,

14 rue d’Issoudun, BP 6744, 45067 Orléans cedex 2, France 2 Laboratoire de Microelectronique de Puissance (LMP), University of Tours, 16 rue P. et M. Curie,

37071 Tours, France 3 ST Microelectronics, 16 rue P. et M. Curie, 37071 Tours cedex 2, France

Received 17 March 2006, revised 13 November 2006, accepted 15 November 2006

Published online 9 May 2007

PACS 82.45.Vp, 85.85.–j

A novel micro-machining technique for silicon deep anisotropic etching and isolating porous silicon

structure formation is developed in this paper. This method combines aluminum thermomigration through

a N type silicon wafer and silicon electrochemical etching in a HF-based solution. Using this technique,

high aspect ratio trenches (1:5) and porous silicon isolating regions have been achieved through the entire

thickness of the silicon wafers. Etch rate measurements have been performed varying the anodization

current density. A maximum value of 22 µm.min–1 has been obtained. Moreover, the porosity behavior

with the current density increase is also discussed.

© 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction

MEMS fabrication faces multiple technological challenges before becoming a commercially viable

technology [1]. One key fabrication process is the deep silicon etching in getting high aspect ratio

structures using chemical wet etching techniques or chemical dry etching (plasma etching) [2]. The

trends concerning these techniques are towards high etch rates, high aspect ratios and high precision

profile control [3]. An etching method that combines consecutively aluminum thermomigration in silicon

and electrochemical etching is presented in this paper. This technique generates trenches or porous

silicon (PS) isolating regions, through the entire thickness of silicon wafers depending on the etching

conditions.

2 The aluminum thermomigration (TGZM)

The thermomigration or Temperature Gradient Zone Melting (TGZM) of aluminum in silicon is based

on the migration of an aluminum-silicon liquid alloy through a silicon wafer, under the influence of a

vertical thermal gradient in a Rapid Thermal Process (RTP) furnace. Then, the molten silicon-aluminum

alloy moves through the silicon wafer with an average velocity of 80 µm/min, leaving a heavily

aluminum doped trail behind it (Fig. 1) [4]. The doping of this area, extending from one face to the

opposite face, was estimated to be about 1019 at.cm–3 [5]. This value corresponds to the solubility limit of

aluminum in silicon.

* Corresponding author: e-mail: sebastien.kouassi@st.com, Phone: +33 247 424 000, Fax: +33 247 424 970

** e-mail: gael.gautier@univ-tours.fr

2176 S. Kouassi et al.: Innovative electrochemical deep etching technique

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Using this technique, we are able to produce silicon samples with an important doping differential

between the P+ regions and the N type bulk silicon. This doping profile sharpness between these two

regions is mainly responsible for the high electrochemical etching selectivity which will be reported.

In our experiments, we used double side polished 6 inch (150 mm) FZ phosphorous doped wafers with a

high resistivity (26-34 Ω.cm), a (100) crystalline orientation and a thickness of 240 µm. Note that the

wafer thickness is not a restrictive point. Experimental samples were prepared using an aluminum

evaporation on one face of the wafer. Two metal stripes of 50 µm wide and spaced with 100 µm made up

the patterned shapes. The size of each duplicated pattern is about 1 mm², for a total aluminum-covered

wafer surface of 10%.

Then, the wafer was placed in a properly designed RTP furnace which ensures a temperature gradient

between the two faces of the wafer. The patterned back surface faces a heat sink, while the front surface

is illuminated by the heating lamps. The temperature is first increased with a short time rise (30 s) from

ambient temperature to process temperature (1300 °C) and then kept nearly constant with a power

control system. The process lasts about 3 minutes for a 240 µm thick wafer. The temperature gradient

(100 °C.cm–1) in the liquid alloy induces a slight silicon concentration gradient causing silicon liquid

diffusion from the hot droplet interface to the cold one. All details about the experimental process and

the equipment are described elsewhere [7]. This phenomenon is comparable to the well known zone

melting technique used for silicon or other material purification [8]. As the lateral diffusion is small, the

resulting doped area is monocrystalline.

Fig. 1 Mechanism of the thermomigration process,

chronological steps from (a) to (c). Al is deposited on

the back surface of the silicon wafer and etched to

design a pattern (a). The wafer temperature is raised well

above the Al melting point and T°front is slightly higher

than T°back. Then, the liquid droplet migrates towards

the front surface (b). Once the thermomigration is

completed and the exceeding Al/Si alloy emerge on the

surface of the wafer (c), a highly doped trail is obtained.

On the cold side of the sample, where the aluminum enters into the silicon wafer, the recrystallization

produces polycrystalline silicon (polysilicon). This layer thickness was about 70 µm in our experiments.

This observation can be linked to the cooling kinetics at the silicon-air interface. Indeed, the cooling rate

in this area is much higher than into the bulk. Moreover, high cooling rates are known to produce very

small grains polysilicon [6]. Notice that nucleation sites can be found only on the sidewalls of the liquid

droplet at the solid-liquid interface. Consequently, there is no crystallization occurring just behind the

silicon-aluminum droplet during its penetration into the silicon bulk.

3 Electrochemical etching of silicon

Although the electrochemical etching of silicon in HF-based electrolytes is known since 1956 [9], the

interest in porous silicon (PS or posi) was initiated quite recently, in 1990, with the discovery of its

electro- and photo-luminescence properties [10]. Nowadays, silicon electrochemistry has shown large

capabilities to produce very high aspect ratio structures in N type and P type. However, although we can

realize very well defined macroporous matrixes, it is very difficult to obtain a single via with vertical

walls using this method [11]. In this work, we take advantage of the etching selectivity between n and p-

type silicon in the dark. Indeed, the silicon oxidation reaction is hole-activated. Consequently, in n-type

without illumination, no holes can be provided to the surface and only high doped p-type regions are

electrochemically attacked [12]. In our case, all the electrochemical etchings were performed in a 6 in. wafer compatible double-tank anodization cell filled with a 30 wt.% HF-H2O electrolyte. A picture of the equipment developed by

phys. stat. sol. (c) 4, No. 6 (2007) 2177

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AMMT is presented Fig. 2. In order to improve the solution wetting, we added 3 ml of a non-ionic surfactant (Triton X-100). Note that all the experiments were conducted in the dark.

Fig. 2 Photograph of the 6 in.

anodization cell used in our

experiments. The two circular

electrodes are made of platinum

and the backside contact is ensured

by the HF solution.

4 Experimental results and discussion

The experiment was performed with various current densities allowing us to take advantage of the two common anodization regimes: the PS formation, and the electropolishing. In the first case, we produced homogeneous PS regions which can go through the entire wafer thickness (Fig. 3a). In the second one, we etched very well defined trenches as we can see in Fig. 3b.

a) b)

Fig. 3 Scanning Electron Microscopy image of TGZM (Temperature Gradient Zone Melting) samples etched with a

total current density of 14.5 mA.cm–2 during 2 hours (a) and 88 mA.cm–2 during 30 min (b). In the first case, we

obtain porous polysilicon regions of about 70 µm deep. In the second case, the attack was stopped just before the

trenches emergence on the opposite face. Then, the walls were smoothed without altering the remaining crystalline

layer in a 5% concentration KOH solution during 2 minutes.

The typical “V” shape of the trench top is due to the narrowing of the doped path at the onset of the aluminum migration. The area corresponds approximately to the polysilicon region. It is worth noting that the n-type area is kept intact. Symmetric structures have been also produced etching alternatively the front and the back side of the wafer with to opposite potentials.

2178 S. Kouassi et al.: Innovative electrochemical deep etching technique

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The etching rates have been also measured as a function of the current density (Fig. 4). Then, we identi-

fied the two main anodization regimes corresponding with the PS formation and the electropolishing. In

the first case, the current density increase induces only a slight rise of the etch rate. Indeed, the porosity

is there the main parameter affected [13]. In the case of the electropolishing, the etching rate increase is

more significant and the maximum value reached with our apparatus is about 22 µm.min–1 .

Fig. 5 Evolution of the high

doped area porosity with the

current density. This porosity is

estimated in two regions: the

70 µm depth polycrystalline layer

and the bulk silicon.

To understand more completely the morphologies observed in our structures, we made porosity

measurements. This parameter was estimated calculating the ratio of the mass loss during the anodization

to the total mass loss [14]. This calculation was performed in the 70 µm deep polysilicon region and in

the underlying P doped bulk silicon. As we can see obviously in the Fig. 5, the porosity behavior with

the current density increase differs with the silicon structure. In accordance with SEM observations

(Fig. 3), we observed an electropolishing regime only of the crystalline silicon for current densities up to

60 mA.cm–2. Indeed, the polysilicon is a material made of many grains, with different crystallographic

orientations, joined with amorphous regions, the grain boundaries. These regions are known to be

depleted of charge carriers. So, the anodization current flows only through the grains, leading to an

original porous structure [15-17]. As a consequence, this material is not sensitive to electropolishing

Fig. 4 Evolution of the etching rate versus the

current density for a 30 wt.% HF solution. We

can distinguish the two common anodization

regimes: the PS formation and the electro-

polishing.

phys. stat. sol. (c) 4, No. 6 (2007) 2179

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because holes can not be provided at the grain boundaries even for high current densities. Indeed, the

maximum porosity reached for a 300 mA/cm² current density is about 90%. We can also note that, even

for very high porosities, the porous poly-silicon region structure, but also its thickness (about 70 µm) and

the confinement of the material, prevent the layer from any crack. On another hand, for the crystalline

region, a transition structure made of porous silicon and cracks is observed for porosities above 80%

without using any particular drying techniques.

Finally, as well as its high trench profile definition, the thermal budget of this technique is very low due

to the short duration of the annealing process (a few minutes). Moreover, it is worth noting that the

maximum measured etching rate can be improved by increasing current densities. This can be achieved

by directly using higher current (a more powerful setup is necessary) or by reducing the surface ratio

between N type silicon and P+ aluminum doped silicon regions. Indeed, in our experiment the total P+

wafer surface is about 10%.

5 Conclusion

We have developed an original and efficient method to prepare trenches or porous regions through the

entire thickness of the silicon wafer. This technique combines aluminum thermomigration in a RTP

furnace and silicon electrochemical etching in a HF solution. The maximum etching rate of 22 µm/min

already obtained for trench realization is very competitive with DRIE (Deep Reactive Ion Etching).

Moreover, as the cost involved in these techniques is very low and the variety of achievable geometries

is relatively large, this method seems to be a promising tool in microelectronics technology, mainly for

MEMS or power applications considering the aluminum contamination of the surface. Further

investigations varying the aluminum-patterned shapes are in progress.

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